The present invention relates generally to a differential amplifying circuit and more particularly to a differential amplifying circuit that may amplify a differential voltage applied to two input terminals and to a multi-stage differential amplifying circuit using the same.
In order to operate a system at a higher speed, large scale integration (LSI) circuits are required to operate at higher frequencies. In order to achieve higher frequencies, signals are transmitted between integrated circuits using small amplitude differential signals. However, it is important to suppress delay differences in order to operate LSI circuits at high frequencies.
In order to achieve a high frequency operation, signal transmission/reception has the following requirements:
1. A transmission signal received external to a chip should have a small amplitude, but can have a wide input voltage range (offset). By allowing the small amplitude, a delay necessitated by charging or discharging a transmission line with respect to an output load can be reduced. Thus, data transfer can be reliably transmitted at high speeds. By allowing a wide range of input, operation can be satisfactory even if noise occurs on the transmission line.
2. Data inputs are synchronized with each other. By synchronizing data inputs, processing inside of the chip can be sped up.
Adverse affects of a difference in delay on a high frequency operation will now be explained with reference to FIGS. 9 and 10.
FIG. 9 sets forth a circuit schematic diagram of a conventional data receiver for a LSI circuit and given the general reference character 900.
Conventional data receiver 900 includes an input buffer block (A and B) and a flip-flop block F/F. Input buffer block A receives data inputs (D1P to D8P and D1N to D8N). Input buffer block B receives clock inputs (CLKP and CLKN). Input buffer block A provides data signals to flip-flop block F/F. The data signals provided by input buffer block A are latched in flip-flop block F/F in synchronism with a clock signal provided by input buffer block B. Input D is a data input into a flip-flop within flip-flop block F/F. Input CLK is a clock input into a flip-flop within flip-flop block F/F.
FIG. 10 is a timing diagram illustrating skews of input signals in conventional data receiver 900. FIG. 10 illustrates a data input signal DATA and a clock input signal CLKP. Data input signal DATA is representative of any data input signals (D1P to D8P and D1N to D8N).
As illustrated in FIG. 10, input buffer A has a delay difference SKEW-1 caused by variations of data input conditions (for example, amplitude and skew of a data input signal (D1P to D8P and D1N to D8N)). Input buffer B has a delay difference SKEW-2 caused by variations of clock input conditions (for example, amplitude and skew of a clock input signal (CLKN and CLKP)). Data input signal DATA has a setup time SETUP in which data input signal must be valid before clock input signal CLKP transitions high to ensure proper operation. Data input signal also has a hold time HOLD in which data input signal DATA must be held after clock input signal CLKP transitions high to ensure proper capture of the data value.
In view of the delay differences (SKEW-1 and SKEW-2) described above, the operation frequency (CLK frequency) of flip-flop block FIF can be expressed in the following equation:
CLK frequency=1/(SKEW-1+HOLD+SKEW-2+SETUP).
Assuming the operating frequency of flip-flop block F/F is 500 MHz and hold time HOLD and setup time SETUP are each 0.3 ns and that SKEW-1 equals SKEW-2, then SKEW-1 and SKEW-2=(2xe2x88x920.3xe2x88x920.3) ns/2=0.7 ns.
Thus, for proper operation of flip-flop block F/F, data input signals (D1P to D8P and D1N to D8N) and clock input signals (CLKP and CLKN) can only have 0.7 ns variations.
Also, in order to achieve a high frequency operation, low voltage differential signaling (LVDS) is used to transmit data from chip to chip. Thus, flip-flop block F/F must include buffers that can operate to receive signals having a small amplitude and within a wide input voltage range. LVDS uses differential data transmission by providing a forward and reverse signal transmitted at a small amplitude and within a wide input voltage range. In this way, a data interface at high speeds that is resistant to noise can be implemented.
Examples of a forward and reverse signal are illustrated in FIG. 11. FIG. 11 is a waveform diagram illustrating an example of a clock signal CLK and a data signal DATA. Data signal DATA includes a forward data signal DATAP and a reverse data signal DATAN. Likewise, clock signal CLK includes a forward clock signal CLKP and a reverse clock signal CLKN. Clock signal CLK and data signal DATA have an amplitude of about 100 mV and are input with a voltage offset within a range of 0 V to 2.2 V.
FIG. 12 is a circuit schematic diagram of a conventional input buffer given the general reference character 1200. Conventional input buffer 1200 is a multi-stage differential amplifying circuit and can operate to receive input signals having a small amplitude within a wide input voltage range.
Conventional input buffer 1200 includes initial stage differential amplifying circuits (SN1 and SP1), next stage differential amplifying circuit SOP, and a p-channel transistor P1. Conventional input buffer 1200 receives a small amplitude input signal at input terminals (H01 and H02) and provides an output at output terminal N01.
Initial stage differential amplifying circuit SN1 has p-channel transistors (P2 and P3) and n-channel transistors (N1 and N2). N-channel transistor N1 has a source connected to ground, a drain connected to node N13 and a gate connected to a drain of p-channel transistor P3 and a gate of n-channel transistor N2. P-channel transistor P2 has a source connected to a drain of p-channel transistor P1, a drain connected to node N13, and a gate connected to input terminal H02. P-channel transistor P3 has a source connected to a drain of p-channel transistor P1, a drain connected to a drain of n-channel transistor N2 and common gates of n-channel transistors (N1 and N2), and a gate connected to input terminal H01.
Initial stage differential amplifying circuit SP1 has p-channel transistors (P4 and P5) and n-channel transistors (N3 and N4). N-channel transistor N4 has a source connected to ground, a drain connected to node N9 and a gate connected to a drain of p-channel transistor P4 and a gate of n-channel transistor N3. P-channel transistor P5 has a source connected to a drain of p-channel transistor P1, a drain connected to node N9, and a gate connected to input terminal H01. P-channel transistor P4 has a source connected to a drain of p-channel transistor P1, a drain connected to a drain of n-channel transistor N3 and common gates of n-channel transistors (N3 and N4), and a gate connected to input terminal H02.
Next stage differential amplifying circuit SOP has p-channel transistors (P6, P7 and P8) and n-channel transistors (N5 and N6). N-channel transistor N6 has a source connected to ground, a drain connected to node NQ50 and a gate connected to a drain of p-channel transistor P8 and a gate of n-channel transistor N5. P-channel transistor P7 has a source connected to a drain of p-channel transistor P6, a drain connected to node NQ50, and a gate connected to node N9. P-channel transistor P8 has a source connected to a drain of p-channel transistor P6, a drain connected to a drain of n-channel transistor N5 and common gates of n-channel transistors (N5 and N6), and a gate connected to node N13. P-channel transistor P6 has a source connected to a power supply VDD and a gate connected to ground.
P-channel transistor P1 has a source connected to a power supply VDD and a gate connected to ground.
Inverter INV1 has an input connected to node NQ50 and an output connected to an input of inverter INV2. Inverter INV2 has an output connected to output terminal N01.
When a differential signal having a small amplitude is input into input terminals (H01 and H02), initial stage differential amplifying circuit SP1 amplifies a potential difference at input terminals (H01 and H02) and outputs a forward amplifying signal at node N9. In the meantime, initial stage differential amplifying circuit SN1 amplifies a potential difference at input terminals (H01 and H02) and outputs a reverse amplifying signal at node N13. Next stage amplifying circuit SOP receives the forward and reverse amplifying signals from nodes (N9 and N13), respectively, and provides further amplification to output an amplified signal to node NQ50. Inverters (INV1 and INV2) provide buffering for the signal at node NQ50 and output a signal which has a full VDD voltage swing at output terminal N01.
In this way, a signal having a small amplitude is amplified in two stages and conventional input buffer 1200 is a differential amplifying circuit which can be operated at a high speed in spite of the small amplitude signal received.
An illustration will now be made of delay differences in conventional input buffer 1200 (a conventional multi-stage differential amplifying circuit) by referring to waveforms from a SPICE (simulation program with an integrated circuit influence) simulation illustrated in FIG. 13.
FIG. 13 is a waveform diagram illustrating the operation of conventional input buffer 1200. The waveform diagram of FIG. 13 illustrates two sets of waveforms. The lower set of waveforms illustrates a case where an input signal at input terminals (H01 and H02) is a 100 mV signal with an offset of 0.0 V (input voltages are 0.0 V to 0.1 V). The upper set of waveforms illustrates a case where an input signal at input terminals (H01 and H02) is a 100 mV signal with an offset of 2.1 V (input voltages are 2.1 V to 2.2 V). All of the waveforms in the upper set have a DC offset of 4.0 V added in order to illustrate different simulation conditions on the same waveform diagram without unduly cluttering the figure. Thus, in the upper set of waveforms ground is at 4.0 V. In order to find the true voltage, 4.0 V must be subtracted from the illustrated voltage output.
Referring now to FIG. 13 in conjunction with FIG. 12, in the upper set of waveforms, when the input voltage is 2.1 V at input terminal H01 and 2.2 V at input terminal H02, the signal amplitude is amplified from 100 mV to 3,044 mV by initial stage differential amplifying circuits (SN1 and SP1), respectively. A delay time from an intersection between input signal at input terminals (H01 and H02) and a rising edge of a signal at node (N9 or N13) is defined as delay tpdr and is 3.044 ns. A delay time from an intersection between input signal at input terminals (H01 and H02) and a falling edge of a signal at node (N9 or N13) is defined as delay tpdf and is 3.453 ns. A delay time (delay tpdr) from an intersection between input signal at input terminals (H01 and H02) and a rising edge (VDD/2 point) of a signal at output terminal N01 is 4.628 ns. A delay time (delay tpdf) from an intersection between input signal at input terminals (H01 and H02) and a falling edge (VDD/2 point) of a signal at output terminal N01 is 4.372 ns.
In the lower set of waveforms, when the input voltage is 0.0 V at input terminal H01 and 0.1 V at input terminal H02, the signal amplitude is amplified from 100 mV to 1,360 mV by initial stage differential amplifying circuits (SN1 and SP1), respectively. A delay time (delay tpdr) from an intersection between input signal at input terminals (H01 and H02) and a rising edge of a signal at node (N9 or N13) is 0.685 ns. A delay time (delay tpdf) from an intersection between input signal at input terminals (H01 and H02) and a falling edge of a signal at node (N9 or N13) is 0.714 ns. A delay time (delay tpdr) from an intersection between input signal at input terminals (H01 and H02) and a rising edge (VDD/2 point) of a signal at output terminal N01 is 2.398 ns. A delay time (delay tpdf) from an intersection between input signal at input terminals (H01 and H02) and a falling edge (VDD/2 point) of a signal at output terminal N01 is 2.172 ns.
A difference in delay caused by the difference in input voltage (offset by 0.0 V and offset by 2.1 V) is 1.684 ns in the initial stage differential amplifying circuits (SN1 and SP1) and is 2.456 ns total at output terminal N01.
Differences in output amplitudes and delay times at node N13 for variations in an offset of an input signal at input terminals (H01 and H02) will now be illustrated in FIGS. 14 and 15. FIG. 14 is a circuit schematic diagram of initial stage differential amplifying circuits (SN1 and SP1). FIG. 15 is a diagram illustrating Vd-Id characteristics of transistors in an initial stage amplifying circuit.
Referring now to FIG. 15 in conjunction with FIG. 14. FIG. 15(1) is a diagram illustrating Vd-Id characteristics of transistors in initial stage amplifying circuit SN1 when an input signal at input terminals (H01 and H02) has an offset of 2.1 V. FIG. 15(2) is a diagram illustrating Vd-Id characteristics of transistors in initial stage amplifying circuit SN1 when an input signal at input terminals (H01 and H02) has an offset of 0.0 V. FIG. 15 illustrates Id-Vd graphs of transistors (P2 and P3), the same line for both high and low input potentials received at their respective gates, Id-Vd graphs of transistor N1, and Id-Vd graphs of diode connected transistor N2. Quiescent operating potentials at node N13 are illustrated at intersections of the Id-Vd line of transistor P2 and transistor N1 and labeled as VN13L (low potential at node N13) and VN13H (high potential at node N13).
When an input signal at input terminals (H01 and 102) has an offset that is higher in potential, the on-resistance of transistors (P2 to P5) is increased. With an increased on resistance, transistor P1 has to provide less current and thus the potential at node N10 is higher. As illustrated in FIG. 15(1), when an input signal at input terminals (H01 and H02) has an offset that is higher in potential, the operating range at node N13 has a wide range. This applies equally to node N9.
In contrast, when an input signal at input terminals (H01 and H02) has an offset that is lower in potential, the on-resistance of transistors (P2 to P5) is decreased. With a decreased on resistance, transistor P1 has to provide more current and thus the potential at node N10 is lower. As illustrated in FIG. 15(2), when an input signal at input terminals (H01 and H02) has an offset that is lower in potential, the operating range at node N13 has a narrow range. This applies equally to node N9.
As noted from the above description, the amplitude of the output signals from initial stage input circuits (SN1 and SP1) at nodes (N13 and N9) are smaller when the input signal at input terminals (H01 and H02) has a smaller voltage offset and is larger when the input signal at input terminals (H01 and H02) has a greater voltage offset.
Furthermore, a P-channel transistor (P2 to P5) may have a lower on-resistance when the input signal at input terminals (H01 and H02) has a smaller voltage offset. With a lower on-resistance the output signals from initial stage input circuits (SN1 and SP1) at nodes (N13 and N9) are sharper or faster. A P-channel transistor (P2 to P5) may have a higher on resistance when the input signal at input terminals (H01 and H02) has a larger voltage offset. With a higher on-resistance the output signals from initial stage input circuits (SN1 and SP1) at nodes (N13 and N9) are more sloped or slower.
A delay value caused by the initial stage differential amplifying circuit (SN1 and SP1) from a full swing of the input signal until an intersection of the complementary output signals at nodes (N13 and N9) is proportional to the offset and the inclination (slope) of the output signals. In other words, the delay value becomes smaller as the offset of the input signal at input terminals (H01 and H02) becomes smaller and the delay value becomes smaller as the inclination (ns/V) of the output signals at node (N13 and N9) is smaller.
From the above-description, it can be seen that a propagation delay value for input stage differential amplifying circuits (SN1 and SP1) is smaller when an offset of the input signal at input terminals (H01 and H02) becomes smaller and is greater when an offset of the input signal at input terminals (H01 and H02) becomes greater.
Delay values for input stage differential amplifying circuits (SN1 and SP1) with respect to a voltage offset in an input signal and an inclination (slope) of an output signal results as follows:
The output signal amplitude when an input signal has a high voltage offset is greater than the output signal amplitude when the input signal has a low voltage offset.
The output signal inclination (ns/V) when an input signal has a high voltage offset is greater than the output signal inclination when an input signal has a low voltage offset.
A delay value for an input stage differential amplifying circuit (SN1 and SP1) when an input signal has a high voltage offset is greater than the delay value when an input signal has a low voltage offset.
By having differences in signal delays in a conventional input buffer circuit (such as conventional input buffer circuit 1200), a greater margin must be designed into the latching of input signals to ensure proper functionality. This reduces overall operating speeds.
The above-described problems have been addressed with the addition of an N-channel transistor between initial stage amplifying circuits (SN1 and SP1) as illustrated in FIG. 16. FIG. 16 is a circuit schematic diagram of a conventional approach to solving delay differences in initial stage amplifying circuits (SN1 and SP1). As illustrated in FIG. 16, a n-channel transistor NND has been added. N-channel transistor has a gate connected to VDD, a first source/drain connected to node N13 of initial stage amplifying circuit SN1 and a second source/drain connected to node N9 of initial stage amplifying circuit SP1.
By connecting n-channel transistor NND between nodes. (N9 and N13) a current flows from the higher potential of nodes (N9 and N13) to the lower potential of nodes (N9 and N13). In this way, a difference in potential between nodes (N9 and N13) i s reduced. By reducing the difference in potential between nodes (N9 and N13) the amplitude of the differential signal carried by nodes (N9 and N13) is reduced.
An amplitude and difference in delay in the initial stage amplifying circuits illustrated in FIG. 16 will now be described with reference to FIG. 16 in conjunction with Vd-Id characteristics of transistors illustrated in FIG. 17. FIG. 17 is a diagram illustrating Vd-Id characteristics of transistors in an initial stage amplifying circuit.
FIG. 17(1) is a diagram illustrating Vd-Id characteristics of transistors in initial stage amplifying circuit SN1 when an input signal at input terminals (H01 and H02) has an offset of 2.1 V. FIG. 17(2) is a diagram illustrating Vd-Id characteristics of transistors in initial stage amplifying circuit SN1 when an input signal at input terminals (H01 and H02) has an offset of 0.0 V. FIGS. 17(1) and 17(2) illustrate a case where n-channel transistor NND is included as solid line waveforms and a case where n-channel transistor NND is not included as dashed waveforms. FIG. 17 illustrates Id-Vd graphs of transistors (P2 and P3), the same line for both high and low input potentials received at their respective gates, Id-Vd graphs of transistor N1, and Id-Vd graphs of diode connected transistor N2.
As illustrated in FIG. 17(1), when an input signal at input terminals (H01 and H02) has a high offset, the on-resistance of transistors (P2 to P5) is increased, thus the potential at node N10 is increased. However, the current flowing from the higher potential of nodes (N9 and N13) to the lower potential of nodes (N9 and N13) through transistor NND serves to reduce the potential swing at nodes (N9 and N13).
In the same manner, when an input signal at input terminals (H01 and H02) has a low offset, the on-resistance of transistors (P2 to P5) is decreased, thus the potential at node N10 is decreased. Also, the current flowing from the higher potential of nodes (N9 and N13) to the lower potential of nodes (N9 and N13) through transistor NND serves to further reduce the potential swing at nodes (N9 and N13).
As noted above, the current flows through n-channel transistor NND in all cases, such that the potential swing at nodes (N9 and N13) is always reduced. Because current always flows through n-channel transistor NND, the output inclination (ns/V) becomes smaller.
An illustration will now be made of delay differences in a conventional input buffer (a conventional multi-stage differential amplifying circuit) using n-channel transistor NND connected between outputs of initial stage amplifying circuits by referring to waveforms from a SPICE simulation illustrated in FIG. 18.
FIG. 18 is a waveform diagram illustrating the operation of a conventional input buffer 1200 of FIG. 12 including the n-channel transistor NND included in FIG. 16. The waveform diagram of FIG. 18 illustrates two sets of waveforms. The lower set of waveforms illustrates a case where an input signal at input terminals (H01 and H02) is a 100 mV signal with an offset of 0.0 V (input voltages are 0.0 V to 0.1 V). The upper set of waveforms illustrates a case where an input signal at input terminals (H01 and H02) is a 100 mV signal with an offset of 2.1 V (input voltages are 2.1 V to 2.2 V). All of the waveforms in the upper set have a DC offset of 4.0 V added in order to illustrate different simulation conditions on the same waveform diagram without unduly cluttering the figure. Thus, in the upper set of waveforms ground is at 4.0 V. In order to find the true voltage, 4.0 V must be subtracted from the illustrated voltage output.
Referring now to FlG. 18 in conjunction with FIG. 12 and FIG. 16, in the upper set of waveforms, when the input voltage is 2.1 V at input terminal H01 and 2.2 V at input terminal H02, the signal amplitude is amplified from 100 mV to 783 mV by initial stage differential amplifying circuits (SN1 and SP1), respectively. It is noted that the signal amplitude is reduced by n-channel transistor NND. A delay time from an intersection between input signal at input terminals (H01 and H02) and a rising edge of a signal at node (N9 or N13) is defined as delay tpdr and is 1.011 ns. A delay time from an intersection between input signal at input terminals (H01 and H02) and a falling edge of a signal at node (N9 or N13) is defined as delay tpdf and is 1.021 ns. A delay time (delay tpdr) from an intersection between input signal at input terminals (H01 and H02) and a rising edge (VDD/2 point) of a signal at output terminal N01 is 3.865 ns. A delay time (delay tpdf) from an intersection between input signal at input terminals (H01 and H02) and a falling edge (VDD/2 point) of a signal at output terminal N01 is 3.793 ns.
In the lower set of waveforms, when the input voltage is 0.0 V at input terminal H01 and 0.1 V at input terminal H02, the signal amplitude is amplified from 100 mV to 947 mV by initial stage differential amplifying circuits (SN1 and SP1), respectively. It is noted that the signal amplitude is reduced by n-channel transistor NND. A delay time (delay tpdr) from an intersection between input signal at input terminals (H01 and H02) and a rising edge of a signal at node (N9 or N13) is 0.552 ns. A delay time (delay tpdf) from an intersection between input signal at input terminals (H01 and H02) and a falling edge of a signal at node (N9 or N13) is 0.543 ns. A delay time (delay tpdr) from an intersection between input signal at input terminals (H01 and H02) and a rising edge (VDD/2 point) of a signal at output terminal N01 is 2.625 ns. A delay time (delay tpdf) from an intersection between input signal at input terminals (H01 and 1102) and a falling edge (VDD/2 point) of a signal at output terminal N01 is 2.532 ns.
A difference in delay caused by the difference in input voltage (offset by 0.0 V and offset by 2.1 V) is 0.478 ns in the initial stage differential amplifying circuits (SN1 and SP1) and is 1.333 ns total at output terminal N01. N-channel transistor NND connected between the outputs (nodes N9 and N13) of initial stage differential amplifying circuits (SN1 and SP1) reduces a difference in delay in the initial stage amplifying circuits (SN1 and SP1) by reducing a magnitude of a signal at the outputs (nodes N9 and N13). By doing so, the initial stage differential amplifying circuits (SN1 and SP1) have a delay difference reduced to as little as 0.478 ns. However, a delay difference at the output terminal N01 of the conventional input buffer is reduced to 1.333 ns (a 0.855 ns improvement). A delay difference of 1.333 ns can still inhibit high frequency signal transfer/reception, and can inhibit overall high frequency performance.
In view of the above discussion, it would be desirable to provide differential amplifying circuit in which high speed may be achieved by reducing a difference in delay time caused by differing offsets of an input signal. It would also be desirable to provide a multi-stage differential amplifying circuit using the same.
According to the present embodiments, a multi-stage differential amplifying circuit may include initial stage differential amplifying circuits. Initial stage amplifying circuits may receive an input signal at input terminals and provide a differential output signal at output nodes. An amplitude controlling transistor may provide a controllable impedance path between the output nodes. An amplitude controlling transistor may have a control gate connected to a current supply node. The controllable impedance path may be controlled so that a magnitude of a differential output signal at output nodes may be more consistent even when an offset voltage of an input signal at input terminals varies. A next stage differential amplifying circuit may receive the differential output signal at output nodes and provide an output signal at an output terminal.
According to one aspect of the embodiments, a differential amplifying circuit may include first and second input terminals coupled to receive an input signal. A current source may be coupled between a power supply and a current supplying terminal. An amplitude controlling transistor may provide a controllable impedance path between a forward and a reverse output terminal. The amplitude controlling transistor may have a gate connected to the current supplying terminal.
According to another aspect of the embodiments, a first input transistor may have a gate coupled to the first input terminal. A second input transistor may have a gate coupled to the second input terminal. The first and second input transistors may be insulated gate field effect transistors (IGFETs).
According to another aspect of the embodiments, the forward and reverse output signals may be provided as an input to a next stage circuit. The next stage circuit may include at least one transistor having a first gate oxide thickness. The first and second input transistors may have a second gate oxide thickness that may be thicker than the first gate oxide thickness.
According to another aspect of the embodiments, the differential amplifier circuit may be included in an input buffer circuit on an integrated circuit.
According to another aspect of the embodiments, a multi-stage differential amplifying circuit may include a first differential amplifying circuit. The first differential amplifying circuit may receive an input signal at first and second input terminals and may provide a differential output signal at a forward and a reverse output terminal. The first differential amplifying circuit may include a first input transistor having a gate coupled to the first input terminal and a second input transistor having a gate coupled to the second input terminal. A current source may be coupled between a first power supply and a current supply node. The current supply node may provide current to the first and second input transistors. An amplitude controlling transistor may have a gate coupled to the current supply node and may provide a controllable impedance path between a forward and a reverse output terminal. A second differential amplifying circuit may be coupled to receive the differential output signal and provide a multi-stage output signal.
According to another aspect of the, embodiments, the first and second IGFETs may have a first conductivity type and the amplitude controlling transistor may be an IGFET having a second conductivity type.
According to another aspect of the embodiments, the first conductivity type may be a p-type and the second conductivity type may be an n-type.
According to another aspect of the embodiments, the first conductivity type may be an n-type and the second conductivity type may be a p-type.
According to another aspect of the embodiments, the second differential amplifying circuit may include at least one IGFET having a first gate oxide thickness. The first and second input transistors may have a second gate oxide thickness that is thicker than the first gate oxide thickness.
According to another aspect of the embodiments, the second differential amplifying circuit may be coupled to operate from a second power supply. The second power supply. may have a lower potential than the first power supply.
According to another aspect of the embodiments, the multi-stage differential amplifying circuit may be included in an input buffer circuit on an integrated circuit.
According to another aspect of the embodiments, a differential amplifying circuit may include a first differential amplifying circuit. The first differential amplifying circuit may be coupled to receive a differential input signal from a first and second input terminal and provide a differential output signal at a forward and a reverse output terminal. An amplitude controlling IGFET may provide a controllable impedance path between the forward and reverse output terminals. A potential at a control gate of the amplitude controlling IGFET may vary as an offset voltage of the differential input signal varies.
According to another aspect of the embodiments, an impedance of the controllable impedance path may be lower when the offset voltage is a first potential than when the offset voltage is a second potential.
According to another aspect of the embodiments, the first differential amplifying circuit may include a first input IGFET and a second input IGFET. The first input IGFET may have a first control gate coupled to the first input terminal and the second input IGFET may have a second control gate coupled to the second input terminal. The first and second IGFETs may have a p-type conductivity and the amplitude controlling IGFET may have an n-type conductivity.
According to another aspect of the embodiments, the first differential amplifying circuit may include a first input IGFET and a second input IGFET. The first input IGFET may have a first control gate coupled to the first input terminal and the second input IGFET may have a second control gate coupled to the second input terminal. The first and second IGFETs may have an n-type conductivity and the amplitude controlling IGFET may have a p-type conductivity.
According to another aspect of the embodiments, a second differential amplifying circuit may be coupled to receive the differential output signal and provide a multi-stage output signal.
According to another aspect of the embodiments, the first differential amplifying circuit may be coupled to operate from a first power supply and the second differential amplifying circuit may be coupled to operate from a second power supply. The first power supply may have a higher potential than the second power supply.